Electronic devices and the like have become more compact in recent years, and as a result there is also an increasing demand for greater compactness in semiconductor devices fitted in electronic devices and the like. Against this background, attention is focusing on technology in which multiple semiconductor chips are stacked in three dimensions rather than being arranged side-by-side in a plane. Among these technologies, a method of connecting chips using through-electrodes (through-substrate vias) running through a semiconductor chip is anticipated to be a technology which can reduce the mounting surface area of a semiconductor package because it does not require a region for routing bonding wires (see Patent Document 2, for example).
Furthermore, a semiconductor chip is generally provided with an electrostatic discharge protection circuit in order to prevent breakage of the internal circuitry caused by static electricity input through an external terminal. This kind of electrostatic discharge protection circuit is also provided in a semiconductor chip having the abovementioned through-electrodes, as described in Patent Document 1, for example. In this case, the electrostatic discharge protection circuit is disposed between the through-electrode placement region and the internal circuitry. Moreover, the through-electrode placement region is also a region for placement of bump electrodes which are provided together with or instead of the through-electrodes, so it can be said that the electrostatic discharge protection circuit is disposed between the bump electrode placement region and the internal circuitry.